Visual Exploration of Simulated FPGA Architecures in Odin II

Field Programmable Gate Array (FPGA) research became more and more important during the last decades. The FPGA technology is being used in many fields and offers the main features scalability, flexibility and the low costs of prototyping. The functionality of FPGA devices is developed using hardware description languages such as Verilog. Those descriptions are translated to boolean circuits which can be programmed on the FPGA devices using Computer Aided Design (CAD) Flows which optimize the circuit for the specific features offered by the FPGA device. The VTR CAD flow is such a workflow consisting of three tools: Odin II, ABC and VPR6.0. In order to handle the growing scale of circuits and features offered by FPGA devices the tools in the CAD flow are being improved constantly. This report describes the development of simulation features within the Odin II circuit visualization software. The software was created in order to visualize the netlist created by Odin II to offer developers exploration functionality. Being able to simulate the circuit in the visualization creates a verification feature which can be used for debugging and research of new FPGA architectures. Another goal of the report is to improve the usability and exploration comfort of the visualization software.